In modern system design, substantial engineering effort is invested in architectural solutions that later prove suboptimal, when not even impractical. This is often the case because the modelling abstraction level adopted during the concept evolution of a system doesn’t allow for capturing early implementation aspects that have a relevant impact on its resource demand, as well as on its performance.

This poster summarises the paper, which will be presented at the SAM 2025. It presents a model-based methodology and an open-source Software platform (DESIRE - Design space Exploration System with Integrated Repurposable Elements) to support it, for early-stage pre-verification of architectural alternatives, aiming to reduce costly late-stage redesigns. Leveraging formally defined and easily composable node abstractions, the proposed framework enables design space exploration (DSE) at a component level without requiring full Register Transfer Level (RTL) implementation. Each node of the network can be adjusted by capturing externally observable behaviour, such as instruction invocation patterns or service delays, while remaining agnostic to internal execution logic.

To improve the fidelity of the estimation models, empirical trace data from detailed simulations or physical systems is back-annotated into node semantics. This process enriches high-level estimation with statistically grounded timing and control-flow characteristics, enabling performance analysis on abstract yet comparable scales. Additionally, we address the reuse of back-annotated data across parameter variants and configurations to support scalable system estimation modelling.

The methodology is demonstrated on an RISC-V-based near-field communication (NFC) data handler, exploring how node-based estimation enables comparative evaluation of early architectural decisions, such as instruction distribution, communication bottlenecks, and contention profiles, before committing to RTL synthesis. While the case study is modest in scope, the framework is designed to scale to complex multi-core architectures and heterogeneous systems. Future extensions may include support for the ITU-T Specification and Description Language, potentially enabling protocol-level behaviours to be integrated within the trace-calibrated framework.