Mon 6 Oct 2025 10:30 - 11:00 at CHS 540 - Session 2: Traceability and Verification

In modern system design, substantial engineering effort is invested in architectural solutions that later prove suboptimal, when not even impractical. This is often the case because the modelling abstraction level adopted during the concept evolution of a system doesn’t allow for capturing early implementation aspects that have a relevant impact on its resource demand, as well as on its performance.

This paper presents a model-based methodology and an open-source SW platform (DESIRE) to support it, for early-stage pre-verification of architectural alternatives, aiming to reduce costly late-stage redesigns. Leveraging formally defined and easily composable node abstractions, the proposed framework enables design space exploration (DSE) at a component level without requiring full RTL implementation. Each node of the network can be adjusted by capturing externally observable behaviour, such as instruction invocation patterns or service delays, while remaining agnostic to internal execution logic.

To improve the fidelity of the estimation models, empirical trace data from detailed simulations or physical systems is back-annotated into node semantics. This process enriches high-level estimation with statistically grounded timing and control-flow characteristics, enabling performance analysis on abstract yet comparable scales. Additionally, we address the reuse of back-annotated data across parameter variants and configurations to support scalable system estimation modelling.

The methodology is demonstrated on an RISC-V-based NFC data handler, exploring how node-based estimation enables comparative evaluation of early architectural decisions—such as instruction distribution, communication bottlenecks, and contention profiles—before committing to RTL synthesis. While the case study is modest in scope, the framework is designed to scale to complex multi-core architectures and heterogeneous systems. Future extensions may include SDL support, potentially enabling protocol-level behaviours to be integrated within the trace-calibrated framework.

Mon 6 Oct

Displayed time zone: Eastern Time (US & Canada) change

10:30 - 12:00
Session 2: Traceability and VerificationSAM Conference at CHS 540

Online

10:30
30m
Talk
Bridging the V-Model: Early Pre-Verification of Digital System Architectures via Estimation and Back-AnnotationRemote
SAM Conference
Christian Seifert Graz University of Technology, Christian Steger Graz University of Technology, Tiberio Fanti NXP Semiconductors Austria GmbH Co&KG
11:00
30m
Talk
Fine-Grained Confidentiality and Authenticity Modeling and Verification for Embedded SystemsRemote
SAM Conference
Jawher Jerray LIUPPA Université de Pau et des pays de l'Adour Pau France, Bastien Sultan Télécom Paris, Polytechnic Institute of Paris, Ludovic Apvrille Télécom Paris
11:30
30m
Talk
Using Concept Traceability to Investigate UML Class Diagram Evolution in Long-Existing FOSS ProjectsRemote
SAM Conference
Zaki Pauzi University of Groningen, Andrea Capiluppi University of Groningen
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